Engineering Plan

technology Plan Engineering Plan SC312 Final blockage 11/7/04 * call* We plan to go across the grassroots multi-cycle processor design as shown in the textbook, as almost as pipelining and jump and plug in. The toughest part of this design depart be the datapath control, for which we volition be using a FSM. The ALU bequeath implement add, sub, and, or, sll, and slt functions though a separate block is typically used for shift operations, we matte that putting sll and srl in the ALU would diversify our design. All other basal functions (lw, sw, lui, beq, bne, j) go out be implement as show in the textbook.

The processor will contend two main stages: commove instructions into store and implement instructions. Special instruction codes will be defined as stall and stop proceeding to work in affair with the FSM. The global reset will set all computer storage and registers to 0, and put the FSM in tear instructions mode. We would akin(predicate) to use one retention module to store some(prenominal) instruct...If you want to get a full essay, order it on our website: Ordercustompaper.com

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